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Performance range - 200MHz (6ns / 5ns@CL=2.5)
Double-data-rate architecture; two data transfers per clock cycle
Bi-directional data strobe (DQS)
Differential clock inputs (CK and CK#)
DLL aligns DQ and DQS transition with CK transition
Auto & self refresh capability (8192 Cycles / 64ms)
Programmable Read latency 2.5 (clock)
Programmable Burst length (2, 4, 8)
Programmable Burst type (Sequential & Interleave)
Edge aligned data output, center aligned data input
Serial presence detect with EEPROM
Power supply - VDD: 2.6Vฑ0.1V(for DDR400)
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